`timescale 1ns / 1ps
module sim(
    );


reg clk,rst_n;
reg      out_en;
initial
begin
    rst_n = 1; 
    #20; rst_n = 0;
    #20; rst_n = 1;
    out_en = 0;
    clk = 1; forever #5 clk = ~clk;
end

parameter CMD_Reset =               8'hFF;
parameter CMD_ReadID =              8'h90;
parameter CMD_ReadStatus =          8'h70;
parameter CMD_ReadPage_C0 =         8'h00;
parameter CMD_ReadPage_C1 =         8'h30;
parameter CMD_ReadPageCache =       8'h31;
parameter CMD_ReadPageCacheCast =   8'h3f;
parameter CMD_ReadMul_C0 =          8'h00;
parameter CMD_ReadMul_C1 =          8'h32;
parameter CMD_ProgPage_C0 =         8'h80;
parameter CMD_ProgPage_C1 =         8'h10;
parameter CMD_ProgPageCache_C0 =    8'h80;
parameter CMD_ProgPageCache_C1 =    8'h15;
parameter CMD_ProgPageMul_C0 =      8'h80;
parameter CMD_ProgPageMul_C1 =      8'h11;
parameter CMD_EraseBlock_C0 =       8'h60;
parameter CMD_EraseBlock_C1 =       8'hD0;
parameter CMD_EraseMul_C0 =         8'h60;
parameter CMD_EraseMul_C1 =         8'hD1;

parameter State_command =   3'b000;
parameter State_adderss =   3'b001;
parameter State_WriteData = 3'b010;
parameter State_ReadData  = 3'b011;
parameter State_Idle =      3'b100;

wire WE_s_m;
wire RE_s_m;
wire CLE_m;
wire ALE_m;
wire[7:0] DQ_m;
wire[7:0] I_DQ_m;
wire RB_m;
wire WP_s_m;
wire[7:0] data_m;
wire[2:0] cmd_m;
wire ready_m;

reg[7:0] data_r;
reg[7:0] O_DQ_m;
reg[2:0] cmd_r;

wire[7:0] val_m;
wire      dv_m;

assign I_DQ_m = DQ_m;
assign DQ_m = out_en ? O_DQ_m : 8'hzz;

assign cmd_m = cmd_r;
assign data_m = data_r;
assign WE_s = WE_s_m;
assign RE_s = RE_s_m;
assign CLE = CLE_m;
assign ALE = ALE_m;
assign DQ = DQ_m;
assign RB = RB_m;
assign WP_s = WP_s_m;

Async_port u_Async_port(
	.WE_s     (WE_s_m     ),
    .RE_s     (RE_s_m     ),
    .CLE      (CLE_m      ),
    .ALE      (ALE_m      ),
    .DQ       (DQ_m       ),
    .RB       (1'b1       ),
    .WP_s     (WP_s_m     ),

    .clk      (clk       ),
    .isEDO    (1'b0      ),
    .rst_n    (rst_n     ),
    .en       (1'b1      ),
    .Cmd      (cmd_m     ),
    .Data     (data_m    ),
    .Val      (val_m     ),
    .DV       (dv_m      ),
    .RB_n     (ready_m   )
);

reg [7:0] test;
reg [7:0] test1;

reg sec;
reg thir;
wire clk2;
wire clk3;
assign clk2 = clk & sec;
assign clk3 = clk & thir;

always @(negedge clk or negedge rst_n) begin
    if (rst_n != 1'b0) begin
        if(test <= 8'h05)begin
            cmd_r <= State_adderss;
            data_r <= test;
            test <= test + 1'b1;
        end else begin
            sec <= 1'b1;
            cmd_r <= State_Idle;
        end
    end else begin
        test <= 8'h00;
        sec <= 1'b0;
    end
end

always @(negedge clk2 or negedge rst_n) begin
    if (rst_n != 1'b0) begin
        if(test1 == 8'h00)begin
            cmd_r <= State_command;
            data_r <= test1;
            test1 <= test1 + 1'b1;
        end else begin
            thir <= 1'b1;
            cmd_r <= State_Idle;
        end
    end else begin
        test1 <= 8'h00;
        thir <= 1'b0;
    end
end

reg[7:0] test3;

always @(posedge clk3 or negedge rst_n) begin
    if (rst_n != 1'b0) begin
        out_en <= 1'b1;
        O_DQ_m <= test3;
        test3 <= test3 + 1'b1;
    end else begin
        test3 <= 8'h03;
    end
end

reg[7:0] readed;
always @(negedge clk3 or negedge rst_n) begin
       if (rst_n != 1'b0) begin
           cmd_r <= State_ReadData;
       end else begin
           cmd_r <= cmd_r;
       end
end

always @(posedge clk3 or negedge rst_n) begin
    if (rst_n != 1'b0) begin
        if (dv_m == 1'b1 && cmd_r == State_ReadData) begin
            readed <= val_m;
        end else begin
            readed <= readed;
        end
    end else begin
           readed <= readed;
    end
end

endmodule